1. Field of Invention
This invention relates to improvements in logic circuits and techniques, and more particularly to improvements in logic circuits and techniques that are compatible with domino logic circuit structures, and still more particularly to improvements in logic circuits and techniques of the type described that are scannable for circuit testing.
2. Background of Invention
Recently, domino logic circuits and design have been receiving the attention of logic circuit designers and fabricators. Domino logic is a precharged, non-inverting family of Complementary Metal Oxide Silicon (CMOS) logic that uses multiple clock phases to effect high-speed operation. Domino logic is faster than standard static logic, but it is more difficult to design because of its increased complexity, primarily in the clocking network.
Typically in domino logic, at least a “precharge” clock phase is used, followed by an “evaluate” clock phase. During the precharge phase, when the clock is low, the output of the cell goes low. During the evaluate phase, when the clock is high, the output of the cell can either transition from a low to a high value or remain at a low value. This is in contrast to standard static logic typically used with CMOS technology. In static logic designs, the output of the cell can arbitrarily rise or fall depending on the input conditioning during normal operation.
Flip-Flops are fundamental building blocks for flow control and pipelining in digital CMOS integrated circuit designs, and have been widely used in domino logic. It has been proposed in some domino logic circuits to use only a pulsed domino latch structures for interfacing with domino logic or standard flip-flops.
In addition, it has been proposed to use full-keeper circuits to prevent the output of the pulsed domino latch from floating when no path to ground or to the supply voltage rail is present. The full-keeper circuit will prevent charge loss due to noise. The keeper circuit prevents the pulsed domino latch from floating when the circuit is not directly driven. Keeper circuits may include, for instance, back-to-back or two cross-coupled inverters. The cross-coupling feedback introduces hysteresis when the pulsed domino latch is directly driven through its inputs. The hysteresis increases the delay through the circuit and the short circuit current power consumed by the circuit.
In addition, in the past, conditional shutoff circuits in the pulse generator have been proposed. The conditional shutoff circuit may be a NAND-logic gate that enables the output of the pulsed domino latch to continue discharging after the sampling window. However, this is not necessary if the duration of the sampling window is long enough.
To interface to static logic, it has been proposed to use an N-C2MOS stage followed by a full-keeper structure as a latching element. However, an output glitch occurs if both the output and data input are at logical high values when the clock signal rises.
Moreover, in the past, scan testing has not been employed in conjunction with the input and output flip-flops or latches, for various reasons. Among the reasons that would argue against the inclusion of scan testing counterintuitive is the notion that to include such scan testing capabilities might undesirably slow down the input or output flip-flop or latch circuits.
What is needed, therefore, is a sequential logic circuit that can interface with a domino circuit and supports scan testing with minimal overhead in terms of performance loss, power consumption, and enlargement of the area footprint.